Synthesizers are designed and used to generate signals in a broad spectrum of frequencies while enabling rapid switching between frequencies selected within that spectrum. Traditional analog synthesizers have been replaced by digital synthesizers, which are generically named Direct Digital Synthesizers (DDS). DDS are increasingly used due to low cost, ease of frequency control and the ability to precisely generate signal with an accurate frequency value selected from a set of possible frequencies. There are available DDS that can, for example, generate signals with frequencies in an operational band of 18 GHz and with resolution of 1 Hz.
A DDS signal generator operates by storing in a memory, in a digital format, selected points representative of a complete cycle of a waveform, and recalling stored points from the memory, in a cyclic manner (to replicate a single cycle repeatedly), to generate the wanted waveform. When the stored waveform values are taken from a sinusoidal waveform then the DDS would generate an approximation of a sinusoidal signal. The rate in which the synthesizer completes a complete cycle of the waveform governs the frequency of the generated wave: the faster the synthesizer completes a cycle, the higher the frequency.
Conventional DDS sinusoidal signal generators are based on Phase Accumulator architecture. This DDS architecture includes a phase accumulator (hereinafter called an accumulator) a mapping device and a digital-to analogue converter (DAC). The accumulator provides an output phase-word value x which is periodically increased by a constant increment value d. The phase-word x is fed to a Sin(x) lookup table (LUT) and is thereby converted into a corresponding sinusoidal amplitude-word value which is the output of the mapping device/LUT. The amplitude value is then fed into a DAC device that generates a corresponding analog signal level. In such devices the output frequency is actually determined by varying the increment value d. The larger the increment value d used, the higher the frequency of the resulting signal. The waveform of the resulting signal resembles a stair-case approximation of the desirable smooth sinusoidal waveform. Deviation from the smooth waveform give rise to unwanted frequency components in the output signal who's magnitudes correspond to the size of the deviations in amplitude and time of the output signal of the DAC. A large number of sample points per waveform period and a high precision of amplitude values are necessary in order to achieve low levels of unwanted frequency components in the resulting output signal.
Naturally, phase accumulator based devices generate output signals with continuous phase/waveform and are therefore inherently non-coherent. This is because the phase of the output signal is determined by the phase word value x of the phase accumulator independently of the selected frequency.
Several techniques for overcoming the non-coherent behavior of the phase accumulator based DDS circuits were previously suggested and implemented in operational circuits. Such techniques are disclosed for example in US patent publication No. 2008/0005213, U.S. Pat. No. 5,063,354 (A) and in U.S. Pat. No. 6,066,967.
As noted above, DDS systems which are based on the phase accumulator architecture inherently provide synthesis of signals with continuous phase which are not phase coherent. According to some techniques, coherent signals are obtained by resetting the phase accumulator at a pre-determined time cycles (predetermined rate).
Other known techniques suggest calculating the required phase value at every frequency switching operation and modifying the phase accumulator value to comply with the calculated phase value.
Multiplying Digital Synthesizer (MDS) is another signal synthesis technique known in the art allowing generation of phase-coherent signals. This technique does not utilize a phase-accumulator but instead it utilizes a phase/time-counter with fixed incremental value. According to this technique, multiple Sine LUTs are stored in a memory module. The Sine LUTs present sampled Sine amplitudes sampled at different rates which correspond to different output frequencies. Different numbers of amplitude words (which are multi-bit values) are stored at each LUT. Accordingly, switching between different output frequencies is performed selecting different LUTs. This technique is described for example in patent publication No. U.S. Pat. No. 6,597,208 and in US patent application 20110199127.